1. Technical Field
The present invention relates generally to the execution of instructions based upon the processing of one or several micro-instructions in a data processing system, and relates in particular to a hardware device for executing programmable instructions by using a set of determined micro-instructions.
2. Prior Act
At the beginning of computers, these ones had small amounts of memory. Therefore, in order to maximize the performance of the computers in the 1960""s, a complex instruction set (well known as CISC) was used to reduce the amount of memory needed. The net effect was an increased efficiency since as a program took less of computer memory, it could retrieve more information for processing.
At that time, memory sub-systems were far slower than the CPU. If one complex instruction encapsulated several simple instructions, the time spent retrieving the instruction from memory was reduced. This was very important insofar as computers were very sequential; the instruction had to be completed before the computer retrieved another instruction from memory processing.
Another key to CISC was microcode. Microcode essentially acted as a translation layer between the instructions and the electronics of the computer. Microcode was a blessing for computer-architects because it made it easier to add new types of machine instructions without having to design new electronic circuits. They could design an architecture family, that is a range of computers sharing the same instruction set.
The net result of microprogramming, apart from the above, was it reduced traffic between the CPU and the memory. It lessened the volume of instructions in the data path making way for more data to move across the path.
But the disadvantage of the CISC data processing systems was that both programmers and compilers used complex instructions only by a quite small percentage. Ever one of these complex instructions only however needs a much greater number of transistors in the chip than the simple instruction, thereby increasing the size of the silicon chip.
In the end of 1970""s, advances in semiconductor technology began to reduce the difference in speed between main memory and processor chips. As memory speed increased and high-level languages displaced assembly language, the major advantages of CISC began to disappear, and computer designers started to study ways computer performance could be optimized beyond just making faster hardware.
One of their key realizations was that a sequence of simple instructions produces the same results as a sequence of complex instructions, but can be implemented with a simpler (and faster) hardware design. Reduced
Instruction Set Computing (RISC) was the result. In a RISC machine, the instruction set contains only simple, basic instructions, from which more complex instructions can be composed. Each instruction has the same length, so that it may be fetched in a single operation. Most instructions complete in one machine cycle, which allows the processor to handle several instructions at the same time. This pipelining is a key technique used to speed up RISC machines.
As a result, the RISC compilers have to generate software routines to perform complex instructions that would have been done in hardware by CISC computers. Since RISC does not have a full set of instructions as in CISC, this requires longer codes to be written and a less optimized sequencing of instructions compared to the optimized CISC instructions. In other words, RISC is not always adapted to all programs, especially when a reduced number of complex instructions is the most frequently used sequence of instructions.
Accordingly, the main object of the invention is to provide a hardware device for processing a set of instructions that better matches the need of each program, allowing the use of simple instructions where necessary and more complex instructions fitting the most frequently used sequence of basic instructions.
Another object of the invention is to provide a hardware device for processing programmable instructions able to run selected sequences of micro-instructions among a limited set of micro-instructions.
The invention relates therefore to a hardware device for parallel processing a determined instruction of a set of programmable instructions having a same format with an operand field defining the execution steps of the instruction, each of the execution steps corresponding to a micro-instruction selected among a plurality of micro-instructions. This device comprises decision blocks being each associated with a specific instruction of the set of programmable instructions, only one decision block being selected by the determined instructions in order to define which are the micro-instructions to be processed for executing the determined instruction, activation blocks respectively associated with the decision macroblocks for running one or several specific micro-instructions, only the activation block associated with the selected decision block being activated to run the specific micro-instructions, and a micro-instruction selection block connected to each activation block for selecting the specific micro-instructions among the plurality of micro-instructions in response to the contents of the operand field of the determined instruction.